1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including transistor elements having a double gate (FINFET) or triple gate architecture.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit elements that substantially determine performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a planar transistor architecture, on the distance between the source and drain regions, which is also referred to as channel length.
Presently, the vast majority of integrated circuits are based on silicon due to substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the past 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and thus allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a basic gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length for a planar transistor configuration requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although usage of high speed transistor elements having an extremely short channel may typically be restricted to high speed applications, whereas transistor elements with a longer channel may be used for less critical applications, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range or 1-2 nm that may not be compatible with requirements for performance-driven circuits.
Therefore, replacing silicon dioxide as the material for gate insulation layers has been considered, particularly for extremely thin silicon dioxide gate layers. Possible alternative materials include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has, therefore, been suggested to replace silicon dioxide with high permittivity materials such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
Although significant advantages may be obtained with respect to performance and controllability of sophisticated planar transistor architectures on the basis of the above-specified strategies, in view of further device scaling, new transistor configurations have been proposed in which a “three-dimensional” architecture may be provided in an attempt to obtain a desired channel width while at the same time maintaining good controllability of the current flow through the channel region. To this end, so-called FINFETS have been proposed in which a thin sliver or fin of silicon may be formed in a thin active layer of a silicon-on-insulator (SOI) substrate, wherein, on both sidewalls, a gate dielectric material and a gate electrode material may be provided, thereby realizing a double gate transistor, the channel region of which may be fully depleted. Typically, in sophisticated applications, the width of the silicon fins is on the order of 10 nm and the height thereof is on the order of 30 nm. In a modified version of the basic double gate transistor architecture, a gate dielectric material and a gate electrode may be formed on a top surface of the fin, thereby realizing a tri-gate transistor architecture.
Thus, FINFET transistor architectures, which may also be referred to herein as multiple gate transistors, may provide advantages with respect to increasing the effective coupling of the gate electrode to the various channel regions without requiring a corresponding reduction in the thickness of the gate dielectric material. Moreover, by providing this non-planar transistor architecture, the effective channel width may be increased so that, for given overall transistor dimensions, an enhanced current drive capability may be accomplished. For these reasons, great efforts have been made in order to provide enhanced transistor performance on the basis of non-planar transistor architectures wherein, however, sophisticated manufacturing processes may conventionally be used, such as selective epitaxial growth techniques, which may result in a significantly reduced overall throughput, since corresponding epitaxial growth processes may typically be performed on a single substrate basis. With reference to FIGS. 1a-1g, a typical conventional process flow for forming a multiple gate transistor is described in more detail in order to more clearly demonstrate the basic configuration and the process techniques involved.
FIG. 1a schematically illustrates a perspective view of a transistor element 100, which may be referred to as a FINFET transistor or multiple gate transistor. As illustrated, the transistor 100 comprises a substrate 101 above which is formed a base layer 102, such as a silicon layer and the like. Moreover, a plurality of fins 110 are formed above the layer 102 and may be comprised of any appropriate semiconductor material, such as silicon, silicon/germanium and the like. As will be explained later on in more detail, the fins 110 may be formed on the basis of an epitaxially grown semiconductor material that may be deposited on the base layer 102, while, in other cases, sophisticated process techniques may be applied in order to provide an SOI configuration wherein the base layer 102 may represent an insulating material, such as silicon dioxide and the like. Furthermore, a gate electrode structure 120 is formed above a central portion of the fins 110, wherein the gate electrode structure 120 may comprise an appropriate gate dielectric material, such as silicon dioxide, in combination with an appropriate electrode material, typically a polysilicon material. Thus, each of the fins 110 in combination with the common gate electrode structure 120 may represent a single transistor cell of the device 100. In the example shown, the fins 110 may have formed thereon a cap layer 112 which may also extend through the gate electrode structure 120, if a top surface of the fins 110 should not act as a channel region. On the other hand, respective sidewalls surfaces 110A, 110B of the fins 110 may represent corresponding channel regions, the conductivity of which is controlled by the gate electrode 120. It should be appreciated that the fins 110 may exhibit an appropriate dopant concentration so as to define corresponding drain and source areas in each of the fins 110, while in other strategies corresponding drain and source regions may be formed in a later stage after connecting the end portions of the fins 110 by growing a further semiconductor material to fill the spacing between the individual fins 110.
FIG. 1b schematically illustrates a top view of the device 100 in an early manufacturing stage. As illustrated, the fins 110 may be formed with lateral dimensions in accordance with the overall design rules for the device 100.
FIG. 1c schematically illustrates a cross-sectional view of the device 100 of FIG. 1b along the line Ic. As illustrated, the fins 110 may extend down to the base layer 102, which may be accomplished on the basis of sophisticated lithography and etch techniques in which a semiconductor material, such as a silicon material and the like, may be etched. Typically, the semiconductor material of the fins 110 may be formed on the basis of epitaxial growth techniques, which may thus result in reduced throughput since this deposition technique may usually be performed on the basis of process tools processing a single substrate at a time. It should be appreciated that, depending on the overall process strategy, a cap material, such as the cap layer 112 (FIG. 1a), may be provided prior to patterning the fins 110 if the top surface of the fins 110 is not to be used as a channel region. Furthermore, prior to or after patterning the fins 110, a basic dopant profile may be established, for instance with respect to defining the basic conductivity type of the fins and the like. This may be accomplished by implantation techniques and/or by incorporating a desired dopant species during the epitaxial growth process for forming the material for the fins 110. Next, the gate electrode structure 120 (FIG. 1a) is formed, for instance by forming an appropriate gate dielectric material, such as a silicon dioxide, which may be accomplished by sophisticated oxidation techniques and the like, followed by the deposition of the gate electrode material, such as polysilicon. After planarizing the electrode material, which may also comprise appropriate materials for forming a hard mask, adjusting the overall optical characteristics on the basis of an anti-reflective coating (ARC) material and the like, the electrode material may be patterned by using a resist mask obtained by lithography and performing an appropriate etch sequence, wherein a high degree of etch selectivity between the gate electrode material and the gate dielectric material may provide integrity of the end portions of the fins 110. For example, well-established process techniques are available for etching polysilicon material selectively to silicon dioxide.
FIG. 1d schematically illustrates a top view of the device 100 after the above-described process sequence and after the removal of any resist materials and other sacrificial materials used for patterning the gate electrode structure 120. As illustrated, the gate electrode structure 120 may have appropriate lateral dimensions so as to cover a central portion of the fins 110 and thereby defining corresponding channel lengths for each of the fins 110. Furthermore, the fins 110 may be covered by a gate dielectric material 121, such as silicon dioxide and the like, as previously explained.
FIG. 1e schematically illustrates a cross-sectional view along the line Ic, as shown in FIG. 1d. As illustrated, the gate electrode structure 120 may comprise a gate electrode material 122 that is formed between the spacing of adjacent fins 110, which are covered by the gate dielectric material 121. In the example shown, it may be assumed that each surface area, i.e., both sidewalls 110A, 110B and a top surface 110T, may act as actual channel regions, which are controlled by the surrounding gate electrode material 122 so that each of the surface areas 110A, 110B and 110T may be considered as being controlled by a dedicated gate electrode. After forming the gate electrode structure 120, drain and source areas may be formed, for instance, by ion implantation, which may include the deposition of a spacer material and patterning the same, if required, while in other cases a semiconductor material may be formed first in order to electrically connect end portions of the fins at both sides of the gate electrode structure 120 in order to provide respective drain and source areas. For this purpose, the end portions of the fins 110 not covered by the gate electrode structure 120 may be exposed by removing the gate dielectric material 121, which may be accomplished by well-established etch recipes, for instance on the basis of hydrofluoric acid and the like. Thereafter, the exposed surface portions of the fins 110 may be prepared for a subsequent selective epitaxial growth process, which may involve well-established cleaning processes and the like. As previously explained, the epitaxial growth process may require sophisticated process tools, which may operate on a single substrate basis, thereby also significantly reducing the throughput of the entire manufacturing flow.
FIG. 1f schematically illustrates a top view of the device 100 after completing the selective epitaxial growth process, thereby forming a silicon material or a silicon/germanium material 131 at both sides of the gate electrode structure 120, thereby defining a drain area 130D and a source area 130S. Thus, as illustrated, the fins 110 may be connected with one end portion thereof to the drain area 130D and may be connected with another end portion thereof with the source area 130S.
FIG. 1g schematically illustrates a cross-sectional view through the drain area 130D wherein it is illustrated that the epitaxially grown material 131 is in direct contact with the fins 110, thereby providing a continuous drain region, the conductivity thereof may be appropriately adapted by ion implantation and the like, wherein corresponding spacer structures may be formed, as previously discussed, to provide a desired dopant concentration gradient in the vicinity of the gate electrode structure 120 (FIG. 1f).
After generating the desired dopant profile in the drain and source areas 130D, 130S, any further processes may be performed, such as anneal processes and the like, followed by the deposition of an appropriate interlayer dielectric material, for instance in the form of silicon dioxide, in combination with an appropriate etch stop material, such as silicon nitride, which may then be patterned so as to obtain contact openings which are subsequently filled with an appropriate conductive material, such as tungsten and the like.
It should be appreciated that a plurality of sophisticated manufacturing techniques are typically used in planar transistor configurations for enhancing overall transistor performance. For example, appropriate strain may be created in the channel region of planar transistors and also sophisticated gate dielectric materials in combination with highly conductive gate electrode materials may frequently be used in order to enhance channel controllability and reduce signal propagation delay. Although the non-planar transistor configuration of the device 100 may provide significant advantages with respect to the overall transistor performance, it is nevertheless highly desirable to also incorporate further performance enhancing mechanisms, which, however, additionally contribute to a further increased overall complexity. That is, due to the epitaxial growth processes which may be required, at least for defining the drain and source areas 130D, 130S, possibly in combination with additional performance enhancing strategies, the resulting manufacturing flow may not be compatible with demands for high throughput, thereby rendering the above-described conventional process techniques less desirable in volume production environments.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.